Chinese tech giant Huawei announced plans for the next generation of its Ascend Chip line at the Huawei Connect 2025 event held in Shanghai this week.
In the keynote speech at the conference, Huawei Committee Vice Chair Eric Xu said 2025 was a “memorable year” and that Deepseek-R1’s debut in January was a turning point for the company. He also acknowledged that China is likely to fall behind the semiconductor manufacturing process node “for a relatively long time.”
The company’s response to tariffs and trade embargo is to advance infrastructure design and technology, and has also decided to open source several large ranges of software, including OpenPanguan Foundation AI Models and Mind Series SDKS.
New rise
The company plans to produce three new series of Ascend Chip: 950, 960 and 970.
The ASCEND 950PR and 950TO are cast from the same die, providing additional support for low-precision data formats including FP8 where the 950 provides PFLOP performance, as well as MXFP8 rated with two PFLOPs. PFLOP is a calculation of 1,000 trillion fluorescent points per second.
It also has better vector processing and more detailed memory accesses, from 512 bytes to 128 bytes chunks.
The Ascend 950 chip offers 2.5 times more interconnect bandwidth than the current Ascend 910c. 950PR will be available in the first quarter of 2026, and the Ascend 950DT launches Q4 2026.
Available in the fourth quarter of 2027 in a year, the Ascend 960 will have 950 twice the number of computing power, memory access bandwidth, memory capacity and interconnect ports. Supports Huawei’s proprietary HIF4 data format.
The most capable chip is the Ascend 970, due for release in Q4 2028. Xu said, “We’re still working on some of that specs, but our general goal is to push all specs much higher.” He said the Ascend 970 series offers 4TB/s of interconnection bandwidth, 8 PFLOPS on the FP4 is possible, and we expect it to have a larger memory capacity.
NPU’s Super Pod
Huawei’s strategy is to provide a raw calculation hyperscalar cluster in the form of a superpod that appears in the form of a Q4 2026 in the form of an Atlas 950 SuperPod equipped with the new Ascend 950DT chip.
The competitor’s NVL144 system (Superpod analog) will be launched late to late 2026, and Huawei claims that the first Superpod will have 56.8 times more NPUs than GPUs on the NVL144, offering nearly seven times more processing power. Despite the scheduled arrival of the NVL576, which NVIDIA is due to release in 2027, the Atlas 950 SuperPod remains a great performance.
Common computing chips
For general computing, Huawei plans to release two models of Kunpeng 950 processors, 96 cores and 192 threads, and 192 cores and 384 threads in the first quarter of 2026, at speeds of two models. Some of them have been called “Wold’s first general purpose computing superpod.” This is the Kunpeng 950-based Taishan 950 SuperPod, which will be available in the first quarter of 2026.
Open Source Connection Protocol
NPU and popular computing superpods use UnifiedBus 2.0, the next iteration of the existing UnifiedBus 1.0. It is the interconnection technology used by the Atlas 900 A3 SuperPod, and was used in over 300 installations this March.
UnifiedBus 2.0 is an open protocol and technical specifications will be released to the developer community soon. UnifiedBus 2.0 is used internally in a new generation of superpods, connecting clusters of superpods to form superclusters.
The first cluster product is the Atlas 950 Super Cluster, which currently offers more than 2.5 times more NPU and 1.3 times more computing power than Xai’s Colossus, the world’s most powerful computing cluster.
In the last quarter of 2027, Huawei is scheduled to launch the Atlas 960 Supercluster. The Atlas960Supercluster integrates over 1 million NPUs and delivers four ZFLOPs on FP4 (Zflops representing 10^21 floating point operations per second). “SuperPods and Superclusters with UnifiedBus are our answers to surge in computing demand both today and tomorrow,” says Xu.
(Image source: Eric Xu, Huawei)
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